1. Field of the Invention
The present invention relates to a data processor and a digital signal processing method of data processing and data transmission in a system having a plurality of data processors connected
2. Description of the Related Art
Hitherto, there are the following two digital signal processing methods in performing data transmission and data processing in a system connecting a plurality of data processors and systematically operating them. According to a first method, a synchronization clock for digital signal processing is distributed from a given clock source to all the data processors forming the system, to synchronize the respective processors to this clock, thereby performing the signal processing. According to a second method, in a system having the data processors cascaded (bead connection or cascade connection), the synchronization clock is superimposed on the transmission data, hence to send the above data from a processor in the prior stage to a processor in the posterior stage, and a synchronization clock is reproduced from the receive data in the posterior processor, thereby performing the signal processing based on the reproduced clock.
In a data processor of performing the data processing by using the above methods, an internal clock of one processor is phase synchronized with a synchronization clock distributed from the outside or a clock reproduced from the transmission data, and predetermined data processing is performed within that processor, according to this clock.
Therefore, it is necessary to fix a reference clock, which is used in each data processor in the above methods, at the same clock frequency, for synchronization among the processors, by using an oscillator of the same frequency in each processor, and in order to change the data speed, each processor needs to take an integer ratio of the reference clocks after synchronization of the processors.
Recently, although a communication speed is more improved according as the data amount increases, it is necessary to change the communication facilities (infrastructure) themselves in order to improve the basic communication speed, but this is not so easy. If using a standardized signal for communication, data transfer speed cannot be changed freely by a user and a maker.
On the other hand, it is much easier to increase the speed of an operation clock of the CPU performing the data processing than the basic communication speed and the CPU clock rate. Since those operation speeds are independent, it is necessary to separately provide an oscillator for an interface of data communication between connected processors and an oscillator for data processing CPU itself, and there is a restriction that the data communication and the data processing are permitted only at a predetermined clock frequency.
Hereinafter, in the specification, a clock used in the data communication between the connected processors will be referred to as “data clock” and a clock used in the data processing of the main body in a particular processor will be referred to as “system clock”.
FIG. 6 and FIG. 7 shows the conventional system structure formed by the above-mentioned methods. FIG. 6 is a structural example of the method (conventional example 1) of receiving a synchronization clock from the outside. This method is used in case of using a signal format of the type incapable of reproducing a clock from the transmission data, like the NRZ (Non Return to Zero) signal method. A synchronization clock is distributed to the respective data processors P1, P2, P3 from a clock creating unit 9 that is an external clock source. In the respective processors, a synchronization clock is supplied to a PLL (Phase Locked Loop) 10, and a clock created by an internal oscillator is phase-synchronized with it, hence to create and output a clock (data clock DCK) for use in the own processor. In the illustrated system, based on the clock, transmission data D is taken from a prior processor P1, and ultimately transferred from processor P2 to the posterior processor P3. The data clock DCK is supplied to a data processing unit 2 and a data processing controlling unit 3 (DSP (Digital Signal Processor) and CPU performing the main processing within processor P2) after multiplying and dividing the clock frequency (DCK′) thereof depending on necessity in a multiplier and divider 11, hence to perform the data processing at the clock frequency.
In FIG. 6 and FIG. 7, DCK indicates a line of the data clock, DCK′ indicates a line of the multiplied and divided data clock, D indicates a line of the transmission data, and D′ indicates a line of the data processed by the data processing unit 2 and the data processing controlling unit 3 in processor P2. A line from the data processing unit 2 to the data processing controlling unit 3 indicates the data given to the data processing controlling unit 3 or the information included in the data. A line from the data processing controlling unit 3 to the data processing unit 2 indicates the data calculated by the data processing controlling unit 3, control signal, or information.
FIG. 7 is a structural example in the method of reproducing a clock from the data with a synchronization clock superimposed there (conventional example 2). In this case, as a transmission coding method of the type capable of reproducing a clock from receive data, various methods including NRZI (Non Return to Zero, Inverted) method are used. In a data receiver 1, a clock is reproduced in the PLL 10 according to the received data from prior processor P1and processor P2 is operated at the above clock or a clock multiplied and divided by the multiplier and divider 11 according to the above clock. When there is no received data, since there is no original data to be synchronized in the PLL 10, a clock in a free running state is used. In case of this method, one oscillator has only to be provided in the PLL 10 in order to do the data transmission and the data processing, and the oscillator can be formed at a low cost.
FIG. 8 shows an example (conventional example 3) formed by using a high speed clock different from a clock used in the data transmission (data clock), as a system clock used within the own processor, in order to speed up the operation within the own processor. In this system, a FIFO (First In First Out) memory 12 is used as the data input and output unit and the data processing is performed by using the system clock (the internal processing clock in FIG. 8). Clock exchange of the data is performed on the input data D and the processing data D from the prior stage P1 and the processing data D′ and the output data U toward the posterior stage P3. At this time, data passing/passed may occur, or data shortage may occur. In order to control this, a state of the memory must be always monitored. When a memory capacity and a system clock are changed, a timing of control and setting must be changed. The memory control is performed by an empty flag, a half flag, and a full flag, as a unit attached to the LSI. A using state of the memory is confirmed by this flag and a separate circuit for counting the number of clocks is provided so to control the memory. When the data D has been stored into the FIFO memory 12 to some degree, it is read out at a stroke and processed, and the data, collected to an overflow avoidable degree, is written into the FIFO memory 12 at the output side.